Stress reduced design of Ceramic mulitlayer circuits


Target of this project is the development of numeric simulation tools to predict and avoid deformations and cracks   during  manufacturing

 of ceramic multilayer circuits and thus reducing costs and improve performance.

Lead time:  01.03.2003 – 30.09.2006

Partner: Micro System  Engineering, Siegert electronic, Kerafol, Ceramtec, W.C. Heraeus, Universität Erlangen-Nürnberg, Fraunhofer Institut für Werkstoffmechanik

Programme: Material Innovation for Industry and Society  

Project sponsor: PT Jülich                                                                                               << zurück